1. Field of the Invention
The present invention relates to a semiconductor memory device such as an EPROM (an erasable programmable read only memory) or an EPL (an erasable programmable logic) circuit provided with a clamping circuit for clamping a voltage supplied onto a word line.
2. Description of the Related Art
The erasable programmable read only memory or the erasable programmable logic circuit have advantages that a user can independently construct a logic circuit. Therefore, the erasable programmable read only memory or the erasable programmable logic circuit is widely used.
In a general semiconductor memory device, a threshold voltage is about 1.5 to 2 volts with respect to a FAMOS transistor (a floating gate avalanche MOS transistor) into which no charge is injected. This threshold voltage is increased by about 3 to 4 volts by the charge injection so that the threshold voltage is about 6 volts after the charge injection.
A shifting amount of the threshold voltage caused by the charge injection is gradually reduced as the size of the erasable programmable read only memory is reduced. Accordingly, when a reading voltage about 6 volts is applied onto word lines in a reading operation of information, a leak electric current flows between a drain and a source of the FAMOS transistor having a high threshold voltage. Therefore, it is difficult to judge values 0 and 1 with respect to information read out of the FAMOS transistors having high and low threshold voltages.
In particular, in the case of the erasable programmable logic circuit, the potentials of gates of half the number of FAMOS transistors commonly connected onto the same bit line are equal to the potential of a power source having a certain voltage. Therefore, a sum of leak electric currents flowing from the respective FAMOS transistors having the high threshold voltage is increased so that the above problem about the judgement of values 0 and 1 is easily caused in comparison with the erasable programmable read only memory.
To avoid such a problem, it is considered to improve writing efficiency with respect to a memory element and secure the amount of an injected charge. However, it is difficult to physically provide such a structure for improving writing efficiency and securing the amount of an injected charge in accordance with the reduction of the size of a semiconductor memory.
Japanese Patent Application Laying Open (KOKAI) No. 62-1192 shows a semiconductor memory device for solving the above-mentioned problems. This device is provided with a clamping circuit for controlling a voltage applied onto a word line and this clamping circuit is disposed every word line. Therefore, this device has a problem that the size of a memory element section constituting the semiconductor memory device is excessively large.